Huawei Semiconductor Head Releases V2 of 'Tao's Law' Paper with Engineering Details
He Tingbo, head of Huawei's semiconductor division, released the V2 version of her paper titled 'Time-Shrinking Theory for Multi-Level Electronic Systems,' also known as 'Tao's Law,' on July 3rd. This updated version, building upon the initial V1 release on May 25th, incorporates extensive engineering implementation details, quantitative measurement data, and product evolution strategies. The paper further refines the scaling theory for the post-Moore's Law era, centered around the time constant τ.
In terms of engineering application, the V2 paper elaborates on the 'gearratio' concept within the core Logic Folding technology. When hybrid bonding spacing approaches the dimensions of top-layer metal wiring, the 3D design space shifts from traditional 'macro-block discrete optimization' to 'cell-level continuous optimization.' This enables globally optimal vertical logic partitioning, overcoming the limitations of conventional 3D stacking that only allows layering by functional blocks. The V2 version also includes new mass production test data, providing specific parameters for the Kirin 2026 and benchmark Kirin 9030Pro, including voltage, frequency, normalized power consumption, area, and power density.
Huawei's release of the V2 'Tao's Law' paper, detailing engineering and empirical data for its time-shrinking theory, signals a strategic effort to advance semiconductor design beyond current Moore's Law limitations. The emphasis on Logic Folding and cell-level optimization suggests a focus on maximizing performance and efficiency through innovative 3D integration techniques. By providing concrete metrics comparing the Kirin 2026 to a benchmark, Huawei aims to validate its theoretical framework and demonstrate tangible progress in chip architecture. This move is particularly significant in the context of global supply chain dynamics and the drive for technological self-sufficiency, positioning Huawei to potentially influence future industry standards and product development pathways.
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