Samsung Electronics to Use 2nm GAA Process for HBM5, Boosting Speed by Over 50%
Samsung Electronics has confirmed that its next-generation HBM5 memory will utilize a 2-nanometer Gate-All-Around (GAA) process. Gu Ja-hyun, head of technology development at Samsung's semiconductor division, stated in an interview on July 27th that HBM5 is expected to deliver speeds more than 50% faster than the current HBM4E. The foundational chips for HBM5 will incorporate the 2nm GAA architecture along with enhanced silicon through-silicon vias (TSV) for greater integration. Samsung Electronics plans to leverage its experience and technical expertise gained from developing 4nm HBM4 base chips to accelerate the adoption of the 2nm process in HBM5. The company aims to expand collaborations with clients across various sectors, including mobile, HBM, AI, HPC, automotive electronics, and robotics. This strategic move is intended to further foster the growth and development of the semiconductor ecosystem.
Samsung's early adoption of a 2nm GAA process for HBM5, ahead of broader industry timelines, signals a strategic push to solidify its leadership in the high-bandwidth memory market, particularly for AI and HPC applications. This aggressive technological advancement aims to capture market share by offering superior performance, potentially creating a competitive advantage over rivals. The company's focus on expanding customer collaborations across diverse sectors indicates a strategy to embed its technology deeply within next-generation product roadmaps. However, the accelerated development cycle for such advanced processes presents significant manufacturing challenges and yield risks. The long-term viability of this strategy will depend on Samsung's ability to manage these complexities while navigating the evolving demands of the AI-driven computing landscape and maintaining cost-effectiveness.
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